Linux has several timers that have varying levels of precision and quirks.

Overflow of timers is listed below, but the timer interrupt schedules the overflow handler when the timer is halfway to its overflow period. Ignoring PIT, this gives the kernel 2.3 seconds to schedule the overflow handler.

TSC (Time Stamp Counter)

Boot Option: clock=tsc

The TSC timer uses the PIT counter and the TSC to determine the current time. TSC was introduced in the Pentium line of processors as the instruction RDTSC.

TSC was never designed to be used as a clock source for multiprocessor systems. When power management features such as frequency scaling act upon the CPUs differently, TSC between the CPUs tends to drift apart making it an unsuitable time source.

Due to its time-correction algorithms, virtual machines using the TSC timer may run too fast.

Jiri Bohac from SUSE Labs was working on a per-CPU TSC patch that would fix this issue with AMD.

PIT (Programmable Interval Timer)

Boot Option: clock=pit

Overflow time: 0.055 seconds

The PIT timer uses the PIT 16-bit counter to determine time. Originally this timer was supplied by the Intel 8253, but now its functionality is usually included in southbridge chipsets.

It also doesn't gain lost time because it doesn't have lost tick correction code. Most problems with clock drift using this timer will manifest as the clock running slower than real time.

PMtimer (ACPI Power Management Timer)

Boot Option: clock=pmtmr

Overflow time: 4.6 seconds

The PMtimer method uses the ACPI's 24-bit timer to determine the correct time. It has smaller time gains than the TSC method.

HPET (High Precision Event Timer)

Boot Option: clock=hpet

Overflow time: approximately 300 seconds (in ICH7/8/9)

This should be the preferred timer, but some platforms or BIOS options do not allow you to enable it. Some BIOS configurations will allow the use of HPET when ACPI 2.0 is enabled.

HPET can cause around 3 seconds of drift per day, so it must be used with an external clock disciplining software such as NTP.

Cyclone

Boot Option: clock=cyclone

Overflow time: 42.9 seconds

The Cyclone timer uses a 32-bit counter on IBM Extended X-Architecture (EXA) chipsets which include computers that use the IBM "Summit" series chipsets (x440, etc). This is available in IA32 and IA64 architectures.

Others

In the future, these timers will be discussed: